Devices based on silicon nanowires have been of recent interest because of novel, and potentially useful, effects associated with their very small size scale as well as the possibility of thermally and mechanically isolating the nanowire structures. For example, gate all-around silicon nanowire transistors have been considered for applications in chemical sensors, optical sensors, various suspended mechanical and thermal elements, and circuit elements exhibiting unusual quantum effects.
Silicon nanowire devices have been produced by various techniques of the prior art, including techniques based on etching with potassium hydroxide, techniques using gold-based or iron-based catalysts, and the growth and surface-dispersal of individual nanowires. However, most of those techniques preclude the possibility of integration with conventional CMOS processes. For example, when potassium hydroxide is used, it is prohibitively difficult to avoid potassium contamination of the silicon substrates, which renders them unusable for CMOS applications.
However, the integration of silicon nanowires on CMOS platforms is very desirable, not least because it offers the possibility of compact and cost-effective packaging of complete electronic hardware systems whose components include nanowire-based sensors.
Hence, there remains a need for CMOS-compatible methods of fabricating silicon nanowires.